CMP (Chemical Mechanical Polishing) is an important elemental technique in semiconductor process and regarded as an indispensable technique in particular to implement a multi-layer wiring structure for high-density wiring.
CMP covers a large variety of objects to process, examples of which include silicon dioxide (SiO2) for an inter layer dielectrics or a buried dielectrics, a metal such as aluminum (Al), copper (Cu), and tungsten (W) used as a wiring layer or a plug to connect such a wiring layer, a barrier metal layer such as tantalum (Ta), tantalum, nitride (TaN), and titanium (Ti) used to prevent metals from diffusing, polysilicon used to form a trench capacitor, and silicon nitride (SiN) to be formed into an etching mask.
In order to carry out optimum polishing to these different kinds of objects, a polishing pad or a polishing composition must be optimized on an object-basis.
In the process of forming wirings in semiconductor process, RIE (Reactive Ion Etching) using a chlorine-based gas is carried, out to a silicon wafer, so that a groove corresponding to a desired wiring pattern and a hole corresponding to a desired plug are formed. A barrier layer made of titanium or titanium nitride is then formed on inner wall surfaces of the groove and the hole, then the entire substrate surface is coated with a wiring metal such as a tungsten layer by plating or the like, so that the groove and the hole are filled with tungsten and then an excess part of the tungsten layer in a region other than the groove and the hole is removed by CMP.
During etching to form such a groove or hole in a silicon wafer, an etching mask is formed on the surface of the wafer, and a silicon nitride layer is used as the etching mask. The etching mask itself is partly removed during etching, and the remaining part of the layer is coated with a wiring metal by plating and must be removed simultaneously with the metal layer by CMP.
The silicon nitride layer used as the etching mask however has a very high mechanical strength, and therefore the polishing speed for the silicon nitride by CMP is low (see Patent Document 1). This could prolong the polishing process.
Because of this problem, the silicon nitride layer is etched away. The etching is carried out by dry or wet process but even in wet process that allows the working time to be relatively shortened requires operation such as heating an etching agent to a high temperature (see Patent Document 2), which prolongs the polishing process and lowers the throughput of the semiconductor process.
Furthermore, a large variety of objects are processed by CMP as described above, and when objects such as a metal layer, an insulating layer, and a silicon nitride layer are processed, it is important to control not only a polishing speed for each of the layers but also selectivity as a ratio between two polishing speeds. Depending on the purpose of processing, the polishing speeds are approximately the same, in other words, the selectivity between them is preferably 1 in some cases, while one of the polishing speeds is preferably higher or lower than the other, in other words, the selectivity between them is preferably greater or smaller than 1 in other cases.
Therefore, the selectivity must be controlled to take various values rather than simply being set to a particular value.
However, in a conventional composition for polishing a silicon nitride layer, two polishing speeds both change in response to a change in the composition, so that it is difficult to control the selectivity to a desired ratio or if possible the polishing speeds themselves are greatly lowered. In other words, sufficient control cannot be achieved.